The present invention relates generally to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device in which a word line contact for connecting a word line to an N+ base layer can be stably formed and a method for manufacturing the same.
Memory devices are typically grouped into volatile random access memory (RAM), in which data is lost when power is interrupted, and non-volatile read-only memory (ROM), in which stored data is maintained even when power is interrupted. Examples of volatile RAM include dynamic RAM (DRAM) and static RAM (SRAM), and examples of non-volatile ROM include flash memory devices such as electrically erasable and programmable ROM (EEPROM).
DRAM is considered an excellent memory device and has many desirable characteristics. However, DRAM must have high charge storing capacity. In order to obtain a high charge storing capacity, the surface area of certain electrodes in the DRAM must be increased; however, if the surface area of the electrodes is increased it is difficult to achieve a high level of integration. Further, in a flash memory device two gates are stacked on each other, and thus a high operation voltage relative to a power supply voltage is required. Therefore, a separate booster circuit is necessary in order to generate the voltage necessary for write and delete operations, which in turn makes it difficult to achieve a high level of integration.
With these constraints in mind, efforts have been made to develop a memory device having a simple configuration and capable of accomplishing a high level of integration while retaining the desirable characteristics of a non-volatile memory device. Recently, phase change memory devices have been gaining popularity. In a phase change memory device, a phase change (crystalline state to amorphous state) occurs in a phase change layer interposed between a bottom electrode and a top electrode when a current is applied to and flows between the bottom electrode and the top electrode. The amorphous and crystalline states have different resistances, and using this phenomenon information stored in a cell can be recognized using the medium of the resistances of the crystalline state and the amorphous state.
An extremely important factor that must be considered when developing a highly integrated phase change memory device is the reduction of programming current. To reduce programming current, a vertical PN diode is used as a cell switching element.
FIG. 1 is a cross-sectional view showing a conventional phase change memory device in which a vertical PN diode is used as a cell switching element. The conventional phase change memory device will be described below.
Referring to FIG. 1, cell switching elements 110 comprising vertical PN diodes are formed on a semiconductor substrate 100. In order to electrically connect the cell switching elements 110 to a word line 160, an N+ base layer 102 is formed in the surface of the semiconductor substrate 100. In order to connect the word line 160 to the N+ base layer 102, a word line contact 150 is formed.
The vertical PN diodes constituting the cell switching elements 110 are composed of stack patterns of an N-type silicon layer and a P-type silicon layer. The word line contact 150 is composed of a first contact plug 152 and a second contact plug 154 which are coaxially connected to each other. In the word line contact 150, after the first contact plug 152 is formed, the second contact plug 154 is formed on the first contact plug 152.
A heater 120 (which serves also as bottom electrode) is formed on each of the cell switching elements 110 comprising the vertical PN diodes, and a stack pattern of a phase change layer 132 and a top electrode 134 are formed on each of the heaters 120. Bit lines 140 are formed over the top electrodes 134 and extend in a direction perpendicular to the word line 160. The bit lines 160 are connected to the top electrodes 134 via top electrode contacts 138.
When compared to a phase change memory device having CMOS transistors as cell switching elements, the phase change memory device having the vertical PN diodes as the cell switching elements 110 has an advantage, in that current flow is high and thus programming current can be reduced. Therefore, the size of cells in the phase change memory can be decreased relative to DRAM or a flash memory device.
In FIG. 1, reference numeral 104 designates a first insulation layer, 112 a second insulation layer, 136 a third insulation layer, and 142 a fourth insulation layer.
However, the above-described conventional phase change memory device is not without problems as is described below.
The first and second contact plugs 152 and 154 of the word line contact 150 that are used to connect the word line 160 to the N+ base layer 102 are formed by depositing tungsten (W) to fill first and second contact holes and then etching back the W. In the course of filling the first and second contact holes with W, seams are likely to be generated in the contact holes. Etching conducted during the etch-back process may then expose the seams to the outside. As a result, when the second contact hole for forming the second contact plug 154 is defined and the first contact plug 152 is etched, a problem occurs in that the contact resistance between the word line 160 and the N+ base layer 102 becomes non-uniform. Specifically, when etch loss of the first contact plug 152 is substantial, the N+ base layer 102 may also be etched causing damage to the N+ base layer 102, and thus the reliability of the phase change memory device can be seriously deteriorated.
The etch loss of the first contact plug 152 and damage to the N+ base layer 102 can be reduced by decreasing the degree of the etch-back; however, in this case, the first contact plugs 152 are not properly separated from each other, whereby a short-circuit can be formed. Therefore, the technique of decreasing the degree to which W is etched back in order to suppress or prevent the etch loss of the first contact plug 152 cannot be adopted.